In recent years, with large capacity and high integration of semiconductor devices, studies on memory cells based on a microfabricating technology in which an integration level doubles for each generation are actively in progress. As one of the technologies for implementing high integration of the semiconductor devices, a technology that reduces a device isolation layer for isolating a plurality of semiconductor devices on a wafer, thereby reducing the size of the semiconductor device, is attracting attention.
A shallow trench isolation (STI) process is a device isolation technology for reducing the size of the semiconductor device. In the STI process, trenches of a predetermined depth are formed in a semiconductor substrate, and an oxide film is deposited in the trenches by chemical vapor deposition (CVD). Then, an unnecessary oxide film is etched by chemical mechanical polishing (CMP), to thereby form a device isolation layer. A local oxidation of silicon (LOCOS) technology that selectively grows a thick oxide film on and/or over a semiconductor substrate to form a device isolation layer is used. However, there is a problem in that a device isolation region is decreased due to lateral diffusion of the device isolation layer and production of a bird's beak. The STI process is widely used for the sake of resolving this problem.
Referring to example FIG. 1A, an STI process for a semiconductor device may initially include sequentially forming pad oxide film 102 and a nitride film 104 on and/or over a semiconductor substrate 100. Next, photoresist is formed on and/or over the nitride film 104 and is patterned by photolithography and etching to correspond to portions of the semiconductor substrate 100 where trenches are to be formed for the STI process. Subsequently, the semiconductor substrate 100 is etched with the photoresist pattern as an etching mask. Thus, trenches for forming a device isolation layer are formed. Next, a thermal oxidation film 106 is formed on and/or over the surfaces of the trenches by oxidation, such as wet or dry etching. At this time, the thermal oxidation film 106 is formed to have a uniform thickness on and/or over the side surfaces and bottoms of the trenches. Next, a liner silicon nitride film 108 is deposited on and/or over the entire surface of the semiconductor substrate 100 including the trenches, and a dielectric filler 110 is deposited in the trenches by CVD. The dielectric filler 110 is a dielectric material that can completely fill the trenches. As the deposition process, for example, PE-CVD (Plasma Enhanced Chemical Vapor Deposition), HDP-CVD (High Density Plasma Chemical Vapor Deposition), or the like may be used.
Next, as shown in example FIG. 1B, the dielectric filler 110 is planarly removed by CMP until the surface of the liner silicon nitride film 108 on the semiconductor substrate 100 where no trench is formed is exposed. Subsequently, the liner silicon nitride film 108, the nitride film 104, and the pad oxide film 102 are removed by etching.
Thus, as shown in example FIG. 1C, a device isolation layer 112 filled with the dielectric filler 110 is formed in the semiconductor substrate 100. The liner silicon nitride film 108 controls stress inside of silicon, i.e., the semiconductor substrate 100, by suppressing an increase in stress due to an increase in volume of the trench when the thermal oxidation film is formed. The liner silicon nitride film 108 prevents doptants, such as boron (B) or the like, from being diffused or prevents H2O or the like from entering inside of the silicon.
According to the method of forming a device isolation layer in a semiconductor device, when stress in the silicon is tensile stress, electron mobility is increased, and NMOS performance is improved. Meanwhile, in a PMOS, when stress in the silicon is compressive stress, hole mobility is increased. From this viewpoint, when the same liner silicon nitride film is applied to the NMOS and PMOS in order to release STI stress, it is impossible to simultaneously improve the characteristics of the NMOS and PMOS. That is, it is necessary to differently apply a liner silicon nitride film to the NMOS and PMOS in order to release stress occurring when the thermal oxidation film is formed.